Design and Implementation of Multiplier Using CMOS Adiabatic Logic

The paper presents a Power consumption plays an important role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopting different design styles. Multipliers play a major role in high performance systems. This project focuses on a novel energy efficient technique called adiabatic logic which is based on energy recovery principle and power is compared by designing a multiplier. CMOS technology plays a dominant role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic style is said to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.